; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -passes=indvars -scev-cheap-expansion-budget=1024 %s | FileCheck %s

; See https://bugs.llvm.org/show_bug.cgi?id=45360
; This is reduced from that (runnable) test.
; The remainder operation is originally guarded, it never divides by zero.
; Indvars should not make it execute unconditionally.

target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-pc-linux-gnu"

@f = dso_local global i32 0, align 4
@a = dso_local global i32 0, align 4
@d = dso_local global i32 0, align 4
@c = dso_local global i32 0, align 4
@b = dso_local global i32 0, align 4
@e = dso_local global i32 0, align 4

define i32 @main() {
; CHECK-LABEL: @main(
; CHECK-NEXT:  bb:
; CHECK-NEXT:    [[I6:%.*]] = load i32, ptr @a, align 4
; CHECK-NEXT:    [[I24:%.*]] = load i32, ptr @b, align 4
; CHECK-NEXT:    [[D_PROMOTED10:%.*]] = load i32, ptr @d, align 4
; CHECK-NEXT:    br label [[BB1:%.*]]
; CHECK:       bb1:
; CHECK-NEXT:    br label [[BB5:%.*]]
; CHECK:       bb13.preheader:
; CHECK-NEXT:    [[DOTLCSSA:%.*]] = phi i32 [ [[TMP0:%.*]], [[BB5]] ]
; CHECK-NEXT:    [[I21:%.*]] = icmp eq i32 [[DOTLCSSA]], 0
; CHECK-NEXT:    br i1 [[I21]], label [[BB27_THREAD:%.*]], label [[BB27:%.*]]
; CHECK:       bb5:
; CHECK-NEXT:    [[TMP0]] = and i32 [[D_PROMOTED10]], [[I6]]
; CHECK-NEXT:    br i1 false, label [[BB5]], label [[BB13_PREHEADER:%.*]]
; CHECK:       bb27.thread:
; CHECK-NEXT:    [[DOTLCSSA_LCSSA:%.*]] = phi i32 [ [[DOTLCSSA]], [[BB13_PREHEADER]] ]
; CHECK-NEXT:    [[I11_LCSSA_LCSSA:%.*]] = phi i32 [ -1, [[BB13_PREHEADER]] ]
; CHECK-NEXT:    store i32 [[DOTLCSSA_LCSSA]], ptr @d, align 4
; CHECK-NEXT:    store i32 [[I11_LCSSA_LCSSA]], ptr @f, align 4
; CHECK-NEXT:    store i32 0, ptr @c, align 4
; CHECK-NEXT:    store i32 0, ptr @e, align 4
; CHECK-NEXT:    br label [[BB32:%.*]]
; CHECK:       bb27:
; CHECK-NEXT:    [[I26:%.*]] = urem i32 [[I24]], [[DOTLCSSA]]
; CHECK-NEXT:    store i32 [[I26]], ptr @e, align 4
; CHECK-NEXT:    [[I30_NOT:%.*]] = icmp eq i32 [[I26]], 0
; CHECK-NEXT:    br i1 [[I30_NOT]], label [[BB32_LOOPEXIT:%.*]], label [[BB36:%.*]]
; CHECK:       bb32.loopexit:
; CHECK-NEXT:    [[DOTLCSSA_LCSSA15:%.*]] = phi i32 [ [[DOTLCSSA]], [[BB27]] ]
; CHECK-NEXT:    [[I11_LCSSA_LCSSA14:%.*]] = phi i32 [ -1, [[BB27]] ]
; CHECK-NEXT:    store i32 [[DOTLCSSA_LCSSA15]], ptr @d, align 4
; CHECK-NEXT:    store i32 [[I11_LCSSA_LCSSA14]], ptr @f, align 4
; CHECK-NEXT:    store i32 0, ptr @c, align 4
; CHECK-NEXT:    br label [[BB32]]
; CHECK:       bb32:
; CHECK-NEXT:    ret i32 0
; CHECK:       bb36:
; CHECK-NEXT:    store i32 1, ptr @c, align 4
; CHECK-NEXT:    br label [[BB1]]
;
bb:
  %i6 = load i32, ptr @a, align 4
  %i24 = load i32, ptr @b, align 4
  %d.promoted10 = load i32, ptr @d, align 4
  br label %bb1

bb1:                                              ; preds = %bb36, %bb
  br label %bb5

bb13.preheader:                                   ; preds = %bb5
  %.lcssa = phi i32 [ %0, %bb5 ]
  %i11.lcssa = phi i32 [ %i11, %bb5 ]
  %i21 = icmp eq i32 %.lcssa, 0
  br i1 %i21, label %bb27.thread, label %bb27

bb5:                                              ; preds = %bb1, %bb5
  %storemerge6 = phi i32 [ 0, %bb1 ], [ %i11, %bb5 ]
  %0 = and i32 %d.promoted10, %i6
  %i11 = add nsw i32 %storemerge6, -1
  %i4 = icmp sgt i32 %storemerge6, 0
  br i1 %i4, label %bb5, label %bb13.preheader

bb27.thread:                                      ; preds = %bb13.preheader
  %.lcssa.lcssa = phi i32 [ %.lcssa, %bb13.preheader ]
  %i11.lcssa.lcssa = phi i32 [ %i11.lcssa, %bb13.preheader ]
  store i32 %.lcssa.lcssa, ptr @d, align 4
  store i32 %i11.lcssa.lcssa, ptr @f, align 4
  store i32 0, ptr @c, align 4
  store i32 0, ptr @e, align 4
  br label %bb32

bb27:                                             ; preds = %bb13.preheader
  %i26 = urem i32 %i24, %.lcssa
  store i32 %i26, ptr @e, align 4
  %i30.not = icmp eq i32 %i26, 0
  br i1 %i30.not, label %bb32.loopexit, label %bb36

bb32.loopexit:                                    ; preds = %bb27
  %.lcssa.lcssa15 = phi i32 [ %.lcssa, %bb27 ]
  %i11.lcssa.lcssa14 = phi i32 [ %i11.lcssa, %bb27 ]
  store i32 %.lcssa.lcssa15, ptr @d, align 4
  store i32 %i11.lcssa.lcssa14, ptr @f, align 4
  store i32 0, ptr @c, align 4
  br label %bb32

bb32:                                             ; preds = %bb32.loopexit, %bb27.thread
  ret i32 0

bb36:                                             ; preds = %bb27
  store i32 1, ptr @c, align 4
  br label %bb1
}
